1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to the structures of a data input/output gate and a write driver.
2. Description of the Prior Art
A system LSI (large scale integrated circuit) having a memory core part (synchronous semiconductor memory device) and a logic circuit controlling the memory core part on the same substrate is developed. The memory core part includes hundreds of data input/output terminals (DQ terminals), for improving the data transfer rate between the same and the logic circuit.
A principal part of such a conventional memory core part is described with reference to FIG. 24. Referring to FIG. 24, symbol MC denotes memory cells, symbols WL0 to WL2 denote word lines, and each of symbols BL(0:n) and /BL(0:n) denotes a plurality of bit lines respectively. Symbols DQ(0), DQ(1), . . . , DQ(7) denote data input/output terminals for inputting/outputting data (or input/output data), and symbols GIO(0), /GIO(0), GIO(1), /GIO(1), . . . , GIO(7), /GIO(7) denote data input/output lines.
A row decoder 914 outputs a word line activation signal for selecting any word line of a memory cell array MA. Another row decoder 915 outputs another word line activation signal for selecting any word line of a memory cell array MB. When either word line activation signal is activated, data is read on any bit line from any memory cell MC or written in any memory cell MC from any bit line. A row decoder (SA)/column decoder 916 outputs a signal for controlling an S/A zone 930.
A GIO line write driver/read amplifier zone 904 includes GIO line write drivers/read amplifiers 910A, 910B, . . . , 910H. Each of the GIO line write drivers/read amplifiers 910A, 910B, . . . , 910H is arranged for each of the data input/output terminals DQ(0) to DQ(7).
The S/A zone 930 includes SA/input/output circuit blocks 902A, 902B, . . . , 902H. Each of the SA/input/output circuit blocks 902A, 902B, . . . , 902H includes a plurality of sets of sense amplifiers and input/output circuits.
A write mask signal WM is input when no data is rewritten in only a certain bit in a write operation. The 1-bit write mask signal WM controls the 8-bit data input/output lines GIO(0), /GIO(0), . . . GIO(7), /GIO(7).
The structure of each SA/input/output circuit block is described with reference to FIG. 25. FIG. 25 shows the S/A input/output circuit block 902A, for example. The SA/input/output circuit block 902A includes a plurality of blocks SAX0, . . . , SAXn. Each of the blocks SAX0, . . . , SAXn includes a sense amplifier SA, an equalization circuit EQ and NMOS transistors TLa, TLb, TRa and TRb.
The sense amplifier SA is activated in response to sense amplifier activation signals SE and /SE. The sense amplifier SA includes a cross-coupled latch amplifying read data read from any memory cell and a circuit transferring write data to any bit line. The equalization circuit EQ equalizes any pair of bit lines in response to a bit line equalization signal BLEQ.
A gate formed by the transistors TLa and TLb is turned on by a signal SHRL for connecting the SA/input/output circuit block 902A with the memory cell array MA. A gate formed by the transistors TRa and TRb is turned on by a signal SHRR for connecting the SA/input/output block 902A with the memory cell array MB. The two memory cell arrays MA and MB share the sense amplifier SA through these gates.
Each of the blocks SAX0, . . . , SAXn further includes an input/output circuit controlled by a column selection signal CSL. For example, the block SAX0 includes an input/output circuit formed by NMOS transistors Q0 and /Q0, and the block SAXn includes an input/output circuit formed by NMOS transistors Qn and /Qn.
The transistors Q0 and /Q0 receive a column selection signal CSL(0) in the gates thereof while the transistors Qn and /Qn receive a column selection signal CSL(n) in the gates thereof.
In a read operation, one of n sense amplifiers SA is selected by the column selection signals CSL(0) to CSL(n). Selected read data is transferred to any pair of data input/output lines. In the write operation, write data is transferred from a sense amplifier selected by the column selection signals CSL(0) to CSL(n) to any bit line. Thus, the data is written in any memory cell.
The structure of each GIO line write driver/read amplifier is now described with reference to FIG. 26. The GIO line write driver/read amplifier 910 shown in FIG. 26 includes a GIO line write driver 950 for the write operation, a read amplifier 952 for the read operation and a GIO line equalization circuit 954.
The GIO line write driver 950 includes inverters IV91 to IV95, NAND circuits NA91 and NA92, NMOS transistors T92 and T94 and PMOS transistors T91 and T93.
The NAND circuit NA91 receives write data WD and a write mask signal /WM obtained by inverting the write mask signal WM in the inputs thereof, and the NAND circuit NA92 receives output of the inverter IV91 inverting the write data WD and the write mask signal /WM in the inputs thereof. The inverter IV92 inverts the output of the NAND circuit NA91, and the inverter IV93 inverts the output of the inverter IV92. The inverter IV94 inverts the output of the NAND circuit NA92, and the inverter IV95 inverts the output of the inverter IV94.
The transistors T91 and T92 are connected between a node receiving a power supply voltage Vcc and a node receiving a ground voltage. The transistors T93 and T94 are connected between a node receiving the power supply voltage Vcc and a node receiving the ground voltage. The gates of the transistors T91 and T92 receive the outputs of the inverter IV93 and IV92 respectively, and the gates of the transistors T93 and T94 receive the outputs of the inverter IV95 and IV92 respectively. The data input/output line GIO is connected with the node between the transistors T91 and T92, and the data input/output line /GIO is connected with the node between the transistors T93 and T94.
The GIO line equalization circuit 954 includes PMOS transistors T95, T96 and T97 receiving a signal GIOEQ in the gates thereof. The transistor T95 is connected between the data input/output lines GIO and /GIO. The transistor T96 is connected between the data input/output line GIO and a node receiving the power supply voltage Vcc, and the transistor T97 is connected between the node receiving the power supply voltage Vcc and the data input/output line /GIO. The pair of data input/output lines GIO and /GIO are equalized in response to the signal GIOEQ.
The read amplifier 952 differentially amplifies data of the pair of data input/output lines GIO and /GIO and outputs read data RD.
In the write operation, the write mask signal /WM is set high. When the write data WD is high, the data input/output line GIO goes high and the data input/output line /GIO goes low. When the write data WD is low, the data input/output line GIO goes low and the data input/output line /GIO goes high.
In the read operation, the write mask signal /WM is set low for bringing the GIO line write driver 950 into a floating state. Read data of a bit line selected by the column selection signal CSL is transferred to the pair of data input/output lines GIO and /GIO. The read amplifier 952 amplifies complementary data received from the pair of data input/output lines GIO and /GIO. Thereafter the GIO line equalization circuit 954 precharges the pair of data input/output lines GIO and /GIO high, to prepare for reading next data.
The write operation/read operation in the conventional semiconductor memory device is described with reference to FIG. 27. At a time t1, the signal GIOEQ and the write mask signal /WM go high. The write data WD is transferred to the pair of data input/output lines GIO and /GIO. The write data WD is high and hence the data input/output line /GIO goes low.
The column selection signal CSL is set high at a time t1-1. The potentials of the pair of bit lines BL and /BL change in response to the pair of data input/output lines GIO and /GIO. Thus, the potentials of the pair of bit lines BL and /BL are inverted so that the write data WD is stored in the selected memory cell (write operation). At a time t1-2, the signal GIOEQ and the write mask signal /WM go low and the pair of data input/output lines GIO and /GIO are precharged for making a transition to the next operation.
After the write operation at a time t2, the signal GIOEQ and the write mask signal /WM are set low for precharging the pair of data input/output lines GIO and /GIO and making a transition to the next operation.
In the read operation, the signal GIOEQ is set high(time t3), for stopping equalization by the GIO line equalization circuit 954. The write mask signal /WM is low.
The column selection signal CSL is set high at a time t3-1, for transferring a low-level signal to the pair of data input/output lines GIO and /GIO from either the bit line BL or the bit line /BL. When the bit line BL is low, for example, the data input/output line GIO is driven low while the data input/output line /GIO is kept high. Thus, a voltage difference arises between the data input/output lines GIO and /GIO. The read amplifier 952 amplifies this voltage difference and outputs the same.
In write masking (performing no data writing), the signal GIOEQ is set high and the write mask signal /WM is kept low similarly to the read operation. The pair of data input/output lines GIO and /GIO are precharged high and hence the potentials of the pair of bit lines BL and /BL are not inverted.
In the conventional semiconductor memory device, however, the pair of data input/output lines GIO and /GIO used for the read operation and the write operation must necessarily be precharged after the write operation. If the pair of data input/output lines GIO and /GIO are not completely precharged, the read amplifier 952 disadvantageously amplifies false data in the next read operation.
A synchronous semiconductor memory device operating in synchronization with an external clock has a function of performing a burst operation for continuously inputting/outputting data. Therefore, the data must be written or read at a determined frequency.
However, the conventional structure requires the precharge time as described above, and hence it is difficult to increase the speed of the operation cycle.